1. Field of the Invention
This invention relates to an output buffer circuit having the function of converting signals into signal voltage levels between different source voltages.
2. Description of the Prior Art
FIG. 5 is a circuit diagram showing a configuration of a conventional output buffer circuit described in, for example, JP-A-7-176084 and is a circuit diagram illustrating a configuration of an input/output circuit of a semiconductor integrated circuit device having a signal level converting function. When an internal signal level is converted from a low voltage to a high voltage, an output buffer of an interface circuit used between semiconductor integrated circuit devices activated at different source voltages makes use of a half-latch type level conversion circuit shown in the drawing and takes a push-pull type output configuration. Incidentally, the semiconductor integrated circuit device having the signal level converting function means one having the function of by-level converting a signal voltage supplied from a device activated at a source voltage inside a large-scale integrated (LSI) circuit into a signal voltage and outputting it to an external circuit activated at a source voltage different from the source voltage for the internal circuit and the function of by-level converting signals supplied from devices activated at external and different source voltages to signal voltages for the internal circuit and transmitting the same to the inside.
In the drawing, reference numeral 7c indicates an input/output control circuit, reference numeral 8 indicates a signal level conversion circuit and reference numeral 9d indicates a buffer circuit. These constitutes an output buffer circuit 10e. Incidentally, a final stage of the buffer circuit 9d constitutes a push-pull circuit 13 composed of a PMOS transistor Q13a and an NMOS transistor Q14. The final stage configures a CMOS (Complementary Metal Oxide Semiconductor) push-pull buffer. Reference numeral 1 indicates an input/output terminal, reference numeral 2 indicates a control terminal, reference numeral 3 indicates an input terminal, reference numeral 11 indicates an input buffer and reference numeral 12 indicates an electrostatic protection circuit. These components designated at numerals 1, 2, 3, 10e, 11 and 12 constitute the aforementioned input/output circuit of semiconductor integrated circuit device.
An internal circuit is electrically connected to the input/output terminal 1 through the input buffer 11. Further, a control terminal 2 for receiving a control signal IN1 outputted from the internal circuit and an input terminal 3 for receiving a control signal IN2 outputted from the internal circuit are electrically connected to the input/output terminal 1 through the output buffer circuit 10e. Further, the control terminal 2 and the input terminal 3 are electrically connected to the input/output control circuit 7c. The input/output control circuit 7c outputs the signals to the signal level conversion circuit 8, and the signal level conversion circuit 8 outputs signals to the buffer circuit 9d through connecting points N15 and N16.
The input/output control circuit 7c and the former half 8a of the signal level conversion circuit 8 are activated by being supplied with a first source voltage V.sub.DD1 corresponding to a source voltage of the internal circuit and a ground potential GND. On the other hand, the latter half 8b of the signal level conversion circuit 8 and the buffer circuit 9d are activated by being supplied with a second source V.sub.DD2 higher than the first source voltage V.sub.DD1 and the ground potential GND. Incidentally, the first source voltage V.sub.DD1 and the second source voltage V.sub.DD2 are supplied from source potential points 4 and 5 respectively and the ground potential GND is supplied from each ground potential point 6.
The operation will next be described.
When the control signal IN1 is of a "H" level (High Level), the connecting points N15 and N16 are respectively brought to an "L" level (ground potential GND) and an "H" level (second source voltage V.sub.DD2) by the signal level conversion circuit 8 even if the output signal IN2 is of an "L" level (Low Level) or the "H" level. Correspondingly, the first signal from the connecting point N15 and the second signal from the connecting point N16 are transmitted via inverter gates G6, G8 and G10, and G7, G9 and G11 of odd-numbered stages, respectively. Therefore, connecting points N17 and N18 are brought to an "H" level and an "L" level respectively. Thus, the gates of the transistors Q13a and Q14 are supplied with signal voltages of the "H" and "L" levels. As a result, both the transistors Q13a and Q14 of the buffer circuit 9d are turned off so that the buffer circuit 9d is brought to a high impedance state with respect to the input/output terminal 1. Thus, the external signal supplied to the input/output terminal 1 is transmitted to the input buffer 11 without its impairment.
On the other hand, when the control signal IN1 is of the "L" level and the output signal IN2 is of the "L" level, the connecting points N15 and N16 are both brought to the "L" level by the signal level conversion circuit 8. In response to this, the transistors Q13a and Q14 of the buffer circuit 9d are turned off and on respectively so that the "L" level is outputted to the input/output terminal 1.
When the control signal IN1 is "L" in level and the output signal IN2 is "H" in level, the connecting points N15 and N16 are both rendered "H" in level by the signal level conversion circuit 8. In response to this, the transistors Q13a and Q14 of the buffer circuit 9d are turned on and off respectively so that the "H" level is outputted to the input/output terminal 1.
FIG. 6 is another circuit diagram illustrating a configuration of a conventional output buffer circuit and shows a configuration of an input/output circuit of a semiconductor integrated circuit device having a signal level converting function similar to that shown in FIG. 5. The circuit configuration shown in FIG. 6 is one in which the buffer circuit 9d shown in FIG. 5 is replaced by a buffer circuit 9e. The circuit configuration shown in FIG. 6 is different from that shown in FIG. 5 in that an inverter gate G12 is additionally provided subsequent to an inverter gate G10 and the PMOS transistor Q13a constituting the push-pull circuit 13 corresponding to the final stage is replaced by an NMOS transistor Q13b. Since other configurations are similar to those shown in FIG. 5, the same parts as those shown in FIG. 5 are identified by like reference numerals and the description of certain common parts will be omitted. Even if such a configuration is adopted, the operation described with reference to FIG. 5 can be performed. Namely, since the NMOS transistor Q13b works in reverse with respect to the PMOS transistor Q13a although a signal level outputted from the inverter gate G10 is inverted by the additionally-provided inverter gate G12, the same logical operation as that shown in FIG. 5 is eventually performed even in the case of the circuit configuration of FIG. 6.
FIGS. 7 and 8 are respectively configurational cross-sectional views of respective pairs of MOS transistors which constitute push-pull circuits corresponding to final stages of conventional output buffers. FIG. 7 is a configurational cross-sectional view of the MOS transistors Q13a and Q14 constituting the push-pull circuit of the buffer circuit 9d. They are PMOS and NMOS types. On the other hand, FIG. 8 is a configurational cross-sectional view of the MOS transistors Q13b and Q14 constituting the push-pull circuit of the buffer circuit 9e. Both transistors are of NMOS types.